Academic Editor: Youssef EL FOUTAYENI
Received |
Accepted |
Published |
Jan 30, 2019 |
Feb 26, 2019 |
Mar 01, 2019 |
Abstract: The SystemC language offers a mature technology to model complex embedded systems made up of software and hardware parts, is became the basic language of the most of industrial productions companies. In spite of the mathematical power of the formal verification methods of the SystemC designs, it knows limitations in terms of the systems length that effect on the speed of the check. In the previous work [1], we proposed our approach the deductions method to verify rapidly the SystemC embedded components based on extracting the executions of equivalence ”paths of equivalence” through which ...